The Spark lab's mission is to build secure systems through
novel architectures with help from operating systems and compilers.
Security work today is spread across the entire stack as well as across mobile devices and cloud servers. Increasingly sensitive programs will shortly run on shiny new hardware that promise to beat Dennard-scaling hurdles but have never met a threat model. All to say, this is a good time for computer architects and systems researchers to jump in.
Spark lab's current projects build a new security-plane for distributed applications. Our projects include building a new instruction-set (ISA) and micro-architecture that translates program-layer security properties into hardware implementations, and a container-orchestrator and compiler that maps distributed web- and micro-services on to our security-ISA. For example, one series of work has been to build hardware boxes that do not leak information, and then use this to put data into boxes instead of applications.
One near-term outcome of our research is to put users back in control of their own data, even if their data is computed on by untrusted applications and infrastructure. In the long term, we'll be on Mars and leave all non-secure computers here.
- Best Paper Nominee, HOST 2019
- Qualcomm Faculty Award, 2018
- Finalist, CSAW Applied Research Competition, 2018
- Best Paper Runner-Up, HOST 2018
- AMD Chair, Department of ECE, UT Austin, 2017-19
- Qualcomm Faculty Award, 2017
- Best Paper Award, ASPLOS 2015
- NSF Career Award, January 2015
- IEEE Micro Top Pick, Honorable Mention, January-February 2015
- Google Faculty Research Award, 2013-14
- Top 10 shortlist for NYU-Poly Best Applied Security Paper Award, 2013.
HOST'19Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems. Shijia Wei, Aydin Aysu, Michael Orshansky, Andreas Gerstlauer, Mohit Tiwari, in Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2019, Tysons Corner, USA. (Best Paper Candidate)
ASPLOS'19Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn. Mark Gallagher, Lauren Biernacki, Shibo Chen, Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Austin Harris, Zhixing Xu, Baris Kasikci, Valeria Bertacco, Sharad Malik, Mohit Tiwari, Todd Austin, in Proceedings of Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2019.
ASPLOS'19Relaxed Hierarchical ORAM. Chandrasekhar Nagarajan, Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari, in Proceedings of Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2019.
ASPLOS'18DATS: Data Containers for Web Applications. Casen Hunger, Lluis Vilanova, Charalampos Papamanthou, Yoav Etsion, Mohit Tiwari, in Proceedings of Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2018, Williamsburg, VA.
HOST'18Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange Protocols. Aydin Aysu, Youssef Tobah, Mohit Tiwari, Andreas Gerstlauer, Michael Orshansky, in Proceedings of IEEE Internation Symposium on Hardware Oriented Security and Trust (HOST), May 2018, Washington DC, USA. (Best Paper Runner-Up)
PETS'18 CSAW Best Applied Security Paper, FinalistPower to peep-all: Inference Attacks by Malicious Batteries on Mobile Devices. Pavel Lifshits, Roni Forte, Yedid Hoshen, Matthew Halpern, Manuel Philipose, Mohit Tiwari, Mark Silberstein in Journal of Privacy Enhancing Technologies Symposium
DATE'18Binary Ring-LWE Hardware with Power Side-Channel Countermeasures. Aydin Aysu, Andreas Gerstlauer, Michael Orshansky, Mohit Tiwari, in Proceedings of Design Automation and Test in Europe (DATE), March 2018, Dresden, Germany.
HPCA'18Secure DIMM: Moving ORAM Primitives Closer to Memory. Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari, Feifei Li, in Proceedings of High Performance Computer Architecture (HPCA), February 2018, Vienna, Austria.
MICRO'16Quantifying and Improving the Efficiency of Hardware-based Mobile Malware Detectors. Mikhail Kazdagli, Vijay Janapa Reddi, Mohit Tiwari, in Proceedings of the 49th International Symposium on Microarchitecture (MICRO), October 2016, Taipei, Taiwan.
USENIX'16Secure, Precise, and Fast Floating-Point Operations on x86 Processors. Ashay Rane, Calvin Lin, Mohit Tiwari, in Proceedings of the 25th Usenix Security Symposium (USENIX), August 2016, Austin, TX.
MICRO'15Avoiding Information Leakage in the Memory Controller with Fixed Service Policies. Ali Shafiee, Akhila Gundu, Manjunath Shevgoor, Rajeev Balasubramonian, Mohit Tiwari, in Proceedings of the 48th International Symposium on Microarchitecture (MICRO), December 2015, Waikiki, Hawaii.
USENIX'15Raccoon: Closing Digital Side-Channels through Obfuscated Execution. Ashay Rane, Calvin Lin, Mohit Tiwari, in Proceedings of the 24th Usenix Security Symposium (USENIX), August 2015, Washington D.C. Short Summary.
ASPLOS'15 Best Paper AwardGhostRider: A Hardware-Software System for Memory Trace Oblivious Computation. Chang Liu, Austin Harris, Martin Maas, Michael Hicks, Mohit Tiwari, Elaine Shi, in Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2015, Istanbul, Turkey.
HPCA'15Understanding Contention-driven Covert Channels and Using Them for Defense. Casen Hunger, Mikhail Kazdagli, Ankit Rawat, Alex Dimakis, Sriram Vishwanath, Mohit Tiwari, in Proceedings of the International Symposium on High Performance Computer Architecture (HPCA), February 2015.
ASPLOS'14 IEEE Micro Top Picks, Honorable Mention, January-February 2015.Sapper: A Language for Hardware-Level Security Policy Enforcement. Xun Li, Vineeth Kashyap, Jason Oberg, Mohit Tiwari, Vasanth Rajarathinam, Ryan Kastner, Timothy Sherwood, Ben Hardekopf, and Frederic Chong, in Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2014, Salt Lake City.
CCS'13 Shortlisted (top 10) for NYU-Poly AT&T Best Applied Security Paper Award, 2013PHANTOM: Practical Oblivious Computation in a Secure Processor. Martin Maas, Eric Love, Emil Stefanov, Mohit Tiwari, Elaine Shi, Krste Asanovic, John Kubiatowicz, Dawn Song, in Proceedings of the ACM Conference on Computer and Communications Security (CCS), November 2013, Berlin, Germany
HASP'14Morpheus: Benchmarking Computational Diversity in Mobile Malware. Mikhail Kazdagli, Ling Huang, Vijay Reddi, Mohit Tiwari in Workshop on Hardware and Architectural Support for Security and Privacy, held in conjunction with ISCA, 2014
HASP'14Memory Bandwidth Reservation in the Cloud to Avoid Information Leakage in the Memory Controller. Akhila Gundu, Gita Sreekumar, Ali Shafiee, Seth Pugsley, Hardik Jain, Rajeev Balasubramonian, Mohit Tiwari, in Workshop on Hardware and Architectural Support for Security and Privacy (HASP), held in conjunction with ISCA, 2014
CARL'13A High-Performance Oblivious RAM Controller on the Convey HC-2ex Heterogeneous Computing Platform. Martin Maas, Eric Love, Emil Stefanov, Mohit Tiwari, Elaine Shi, Krste Asanovic, John Kubiatowicz, Dawn Song, in Workshop on the Intersections of Computer Architecture and Reconfigurable Logic, 2013
I enjoy building new hardware-software systems that enforce well-defined security properties. Before joining UT, I received my PhD in UC Santa Barbara in 2011, and then worked as a post-doc at UC Berkeley.
My research interests span machine learning and program languages.
I am interested in designing secure processors and accelerators and prototyping them on a FPGA.
I am interested in using machine learning and operating systems to build privacy-preserving systems.
I build side channel defenses and intelligent adversary models to quantify and bound theoretical information leakage.
My research interests include compiler transformations for improving security, side-channel defenses, and public policy implications of cybersecurity.
I study the design, optimization, and secure implementations of next-generation cryptosystems. Before joining UT as a post-doc, I received my PhD from Virginia Tech in 2016.
I am interested in designing provably secure systems using cryptography and formal methods.
I am interested in leveraging machine learning techniques to solve security problems in architecture.
I am interested in understanding tradeoffs between system performance and security and leveraging strengths from all layers towards a high-performance secure system.
My research interests lie in the domains of computer architecture, microarchitecture and security. I am eager to learn more about how hardware and software can interact to guarantee better data privacy.